Buried high sheet resistance structure for high density integrated circuits with reach through contacts

ABSTRACT

A high sheet resistance structure for high density integrated circuits and the method for manufacturing such structure is given. The structure includes a silicon region separated from other silicon regions by a dielectric barrier surrounding the region. A resistor of a first conductivity, for example, N type, encompasses substantially the surface of the silicon region. Electrical contacts are made to the resistor. A region highly doped of a second conductivity, for example, P-type, is located below a portion of the resistor region. This region of second conductivity is connected to the surface. Electrical contacts are made to this varied region for biasing purposes. A second region within the same isolated silicon region may be used as a resistor. This region is located below the buried region of second conductivity. Alternatively, the described resistor regions can be connected as transistors. This allows the formation of a standard masterslice which can be personalized at a late stage in the manufacturing to either resistors or transistors in all or a portion of the standard regions.

BACKGROUND OF THE INVENTION

The invention relates to resistance structures for high density integrated circuits and to methods for forming a highly dense masterslice structure which may be advantageously utilized to form resistors or transistors in an integrated circuit structure.

CROSS REFERENCE TO RELATED APPLICATIONS

N. Anantha et al Patent Application, Ser. No. 844,767, U.S. Pat. No. 4,159,915 issued July 3, 1979, filed simultaneously with this application, entitled "Method for Fabricating Vertical NPN and PNP Structures and the Resulting Product".

N. Anantha et al Patent Application, Ser. No. 844,769, filed simultaneously with this application, entitled "High Performance Bipolar Device and Method for Making Same".

DESCRIPTION OF THE PRIOR ART

In the monolithic integrated circuit technology, it is usually necessary to isolate various active and passive elements from one another in the integrated circuit structure. These devices have been isolated by back-biasing PN junctions, partial dielectric isolation and complete dielectric isolation. The dielectric materials used have been silicon dioxide, glass, and so forth. The preferred isolation for these active devices and circuits particularly as integration density has increased is some form of dielectric isolation. The dielectric isolation has substantial advantage over the PN junction isolation because it allows the abutting of the circuit elements against the isolation and thereby results in greater density of packing of the active and passive devices on the integrated circuit chip. Dielectric isolation reduces associated parasitic capacitance and hence improves circuit performance.

Dielectric isolation techniques of today usually involve the formation of grooves or channels in a silicon body and the filling thereof with a dielectric material. One technique is to form the openings by chemical etching and is described fully in E. Kooi U.S. Pat. No. 3,970,486, Clevenger U.S. Pat. No. 3,534,234, Peltzer et al U.S. Pat. No. 3,648,125 and I. Magdo et al U.S. patent application Ser. No. 150,609, filed June 7, 1971. Another technique involves selectively forming an epitaxial layer with grooves or openings therein and is described in V. Y. Doo U.S. Pat. No. 3,386,865 and "A Composite Insulator-Junction Isolation" by R. E. Jones et al, published in Electrochemical Technology, Vol. 5, No. 5-6, May-June 1967, pp 308-310. Another technique for forming grooves is shown by Hochberg U.S. Pat. No. 3,966,577, T. Kaji et al U.S. Pat. No. 3,997,378, and S. A. Abbas, IBM TDB, Vol. 20, No. 1, p. 144 June 1977, and Bondur et al U.S. patent application Ser. No. 824,361, filed Aug. 15, 1977, uses reactive ion etching.

Isolated pockets of monolithic silicon is the result of the isolation process described in the previous paragraph. Active devices, such as bipolar transistors, field effect transistors, and passive devices such as resistors, diodes, and so forth, may then be formed in these monocrystalline silicon pockets. The essential steps in the formation of silicon planar devices may be seen, for example, in the book "Modern Microelectronics" by Max Fogiel published by Research and Education Assoc., 342 Madison Avenue, New York, N. Y. 10017, 1972 (See particularly pages 463-472). Briefly, the process involves obtaining, for example, a P substrate of silicon, oxidizing the surface opening a window in the silicon dioxide using standard photolithography and etching techniques, diffusing an N+ buried region through the opening. The silicon dioxide is removed and an epitaxial layer of N-type silicon is grown thereover. During the epitaxial layer growth there is some outdiffusion of the buried layer into the epitaxial layer. The buried layer is destined to become the subcollector of an NPN transistor in this example. Another silicon dioxide layer is grown on the surface of the epitaxial layer, openings for isolation diffusion in the silicon dioxide are formed by photoresist and etching techniques, and the isolation diffusion or dielectric isolation is formed to isolate pockets of monocrystalline silicon. Openings are formed in the silicon dioxide coating where the base of the NPN transistor is to be formed and any P-type resistors are to be formed, and a P-type diffusion forms PN junctions in the N epitaxy layer. The surface is reoxidized and the use of photolithography and etching techniques made to open the regions destined to be the emitter and the collector reach-through. The emitter and reach-through diffusions are made. The surface is again oxidized. Openings are made in the silicon dioxide mask using conventional photolithography and etching techniques for the ohmic contact purposes. The entire surface is metallized, such as with aluminum film, and using conventional photolithography and etching techniques, the interconnections are formed through the etching away of the metal film.

Diffused resistors are generally used in the manufacture of integrated circuits, however, they are normally formed during the base diffusion of a bipolar transistor integrated circuit structure. This is illustrated in the previous paragraph and in Schlegel U.S. Pat. No. 3,591,430, S. P. Davis U.S. Pat. No. 3,772,097, G. K. Lunn U.S. Pat. No. 3,700,977 and P. W. Robertson U.S. Pat. No. 3,959,040. This type of resistor has disadvantages when it is desired to go to greater density in the integrated circuits. Some of the disadvantages are that the diffusion depth has to be deep enough to allow another diffusion of opposite polarity, for example, the emitter. Furthermore, the base region normally requires doping around 10¹⁸ atoms/cm³. High value resistors cannot be made at high doping levels of 10¹⁸ atoms/cm³. This type of resistor is not suitable for low power, high density IC's. The resistors and structures described herein have high value, tight tolerance resistance sheet rhos. This is advantageous to high density IC and results in low cost per logic circuit.

Resistors have also been formed in the N epitaxy region such as is shown by R. A. Pedersen, U.S. Pat. No. 3,860,836. In this patent the resistor is isolated from other devices by P-N junction isolation. This type of device has the disadvantage when a highly integrated structure is desired of high valued N- epitaxy resistors. Autodoping from adjacent pockets (N+ or P+) will modulate the N- layer during epitaxial layer growth. The effect will be a poor tolerance sheet resistance (usually plus or minus 40%). Further, the epitaxial layer is necessarily very thick for fabricating a transistor. Hence, the sheet rho cannot be high even without the autodoping effect.

A wide variety of diffused, ion implanted or epitaxial grown regions of various N and P conductivities in various configurations have been formed in isolated monocrystalline silicon pockets. Examples of this are shown in the patents and publications cited above. Further citations of this type of structure is shown by M. V. Vora U.S. Pat. No. 3,703,420 and W. T. Matzen et al U.S. Pat. No. 3,982,266 which show junction isolation. R. D. Schinella et al U.S. Pat. No. 3,919,005 and I. E. Magdo et al U.S. Pat. No. 3,954,523 show dielectric isolated monocrystalline silicon pockets.

SUMMARY OF THE PRESENT INVENTION

In accordance with the present invention, a resistance structure for high density integrated circuits is described. The resistance structure includes a silicon region separated from other silicon regions by a dielectric barrier. A resistor of one conductivity encompasses substantially the surface of the silicon region. A region of the opposite conductivity is located below a portion of the silicon region and a reach-through connects the buried region to the surface. The electrical contacts are made to the resistor. Other electrical contacts are made to the buried regions which is utilized for biasing purposes to isolate the resistor region from the remaining lower portion of the silicon body. A second resistor can be made in the same silicon region as the first resistor. This second resistor is located below the buried region with reach-throughs to connect the second resistor to the surface of the silicon region where electrical contacts can be made thereto.

An integrated circuit structure is also described. This structure is composed of silicon regions separated from like silicon regions by a dielectric barrier. Each of the silicon regions include a base region of one conductivity, a second region over the base region of a second conductivity, a third region of the first conductivity buried within the second region and a reach-through region of the first conductivity connecting the surface of the silicon regions with the third region. This integrated circuit structure is useful as a masterslice which can be personalized at the time of forming electrical contacts to the regions as either a transistor or a resistor with electrical connections between these two alternate types of devices.

Methods are also described for fabricating the resistor structure for integrated circuits and the masterslice integrated circuit structure. A monocrystalline silicon body is provided which includes a substrate of the first conductivity and the region of a second conductivity thereover. A pattern of dielectric regions are formed in this monocrystalline body which isolate surface regions of the body from one another. A buried region is formed of the first conductivity within the region of the second conductivity and a reach-through region of the first conductivity is formed to connect the surface of the silicon region to the buried region. Electrical contacts are then made to the various regions within the isolated silicon regions to fabricate, as desired, resistors and/or transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-4 illustrate the method of fabricating and the final structure of one form of a resistor of the present invention;

FIGS. 5 and 6 illustrate the final structure of a second form of the resistor of the present invention;

FIGS. 7 and 8 are circuit schematics of the two resistors illustrated structurally in FIGS. 5 and 6;

FIG. 9 is a third embodiment of the integrated circuit structure which is useful as a vertical transistor; and

FIG. 10 is a circuit schematic of the NPN transistor of the FIG. 9 structure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now more particularly to FIGS. 1-4, the manufacturing steps for one form of the invention involves starting with the wafer or substrate 10 of P- silicon monocrystalline material. The substrate 10 is fabricated, for example, by pulling a monocrystalline rod from a suitable melt containing a P-type material such as boron and using a seed crystal having a <100> crystallographic orientation. The resulting rod is then sliced into very thin wafers which also have the surface crystallographic orientation of <100>. The P- silicon wafer has preferably a resistivity of 10-20 ohms centimeter.

The structure is then placed in an epitaxial growth chamber wherein an epitaxial layer 12 is grown on the surface of the substrate 10. The epitaxial layer may be any desired thickness, however, for the purpose of high performance device of the type involved in the present invention, the thickness should be less than about 2 micrometers. The preferred thickness of the epitaxial layer is about 1.2 micrometers. Layer 12 is grown onto the substrate 10, by conventional techniques such as the use of SiCl₄ H2 or SiH₄ /H₂ mixtures of about 1000° to 1200° C.

The next series of steps is directed to the technique for reactive ion etching of the silicon structure. A silicon dioxide layer (not shown) is formed by conventional techniques of either thermal growth at a temperature of 970° C. in wet or dry oxygen ambient or by chemical vapor deposition. Other mask materials can also be used such as silicon nitride and aluminum oxide or combinations thereof. It is preferred that a 1000 to 3000 A silicon dioxide coating be formed by a chemical vapor deposition of using a mixture of silane and N₂ O at 800° C. in a nitrogen ambient. Suitable openings are formed by conventional photolithography and etching techniques in the silicon dioxide layer where the isolation regions are to be formed. The structure is then put into a silicon reactive ion etching ambient. The process for this reactive ion etching may be more fully understood by reference to the J. N. Harvilchuck et al patent application Ser. No. 594,413, filed July 9, 1975, for "Reactive Ion Etching of Silicon". The RF induced plasma is reactive chlorine, bromine or iodine specie as specified in the Harvilchuck et al patent application. The thickness of the masking layer is between 2000-20,000 Angstroms, the exact thickness depending on the depth requirement of the silicon groove. A precise description of the RF discharge apparatus is given in the beforementioned patent application. The reactive ion etch or plasma ambient is preferably a combination of an inert gas such as argon and a chlorine specie. Application of suitable power is in the order of about 0.1-0.75 watts/cm² from an RF voltage source which produces sufficient power density to cause the reactive ion etching operation of silicon to be carried out at the suitable rate. The desired result of the etching is the shallow opening wherein the opening or channel partially penetrates the P-base region 10. This results in the FIG. 1 structure.

The next step in the process is to thermally oxidize the openings or channels by subjecting the body to an oxidation ambient which may be, for example, 970° C. in wet oxygen. The body is subjected to the ambient for about 10 to 30 minutes to produce the preferred silicon dioxide thickness within the opening or channel between about 500-2000 Angstroms. The purpose of the thermal oxide is to assure good silicon dioxide interface properties, the qualities of which are usually not as good with chemical vapor deposited dielectric material. Good quality dielectric material is necessary to permit the subsequent abutting of diffused junctions against the dielectric isolation. The complete filling of the opening with a suitable dielectric material is accomplished using vapor deposited silicon dioxide. The details of this process is described in the beforementioned Bondur et al patent application.

It may be preferred in some instances, prior to pyrolytic deposition step to ion implant boron ions through the bottom of the oxide at the bottom of the channel. This causes the formation of the P+ region underneath the isolation region which prevents the P- region under the isolation region from inverting to an N type material.

The pyrolytic silicon dioxide is deposited in a thickness of preferably 2 to 3 micrometers. The preferred filling process is a chemical vapor deposition of silicon dioxide using gas mixtures of CO₂ /SiH₄ /N₄ or N₂ O/SiH₄ /N₂ between 800 and 1000° C. The typical deposition rate is to the order of 50-100 Angstroms per minute.

The next step is the reactive ion etching of the chemical vapor deposited silicon dioxide layer to remove excess silicon dioxide from the surface. The system used for this process would be of the low pressure sputter etch type system with the wafer positioned on a silicon cathode cover plate. A fluorinated hydrocarbon such as CF₄ would type system with the wafer positioned on a silicon cathode cover plate. A fluorinated hydrocarbon such as CF₄ would be used as an etchant so that an SiO₂ /Si ratio of approximately 1:1 results. The gas pressure could run from 10 to 70 micrometers with gas flow rates of 2 to 50 cc/min. The RF power level runs from 0.1 watts/cm².

FIG. 2 now shows the complete isolation of the desired monocrystalline silicon regions by means of dielectric isolation regions 14. The surface of the body is reoxidized by growth of 0.1 to 0.2 microns of thermal silicon dioxide to bring the silicon dioxide layer 16 to the desired thickness.

Referring now to FIG. 3, the buried implant for the PN junction isolation of the resistor is accomplished. Photolithography and etching techniques are utilized to expose and develop the photoresist pattern and then remove portions of the photoresist areas to expose the regions wherein P+ type ion implantation is to be accomplished. The structure is then placed in a suitable ion implantation apparatus wherein a boron ion implantation is accomplished using 200 to 500 KeV and 5×10¹⁴ atoms/cm². It should be noted that a thin silicon oxide coating of 250 to 300 Angstrom units is allowed to remain on the surface of the structure. This silicon dioxide coating has the function of a screen for the ion implantation step. The result of the process is the P type buried region 18. The reach-through diffusion for the buried P region 18 is accomplished by applying a simple photoresist exposing, developing and etching the photoresist to expose the regions which are to be the P reach-through through the photoresist. The structure is again placed in the suitable ion implantation apparatus and a boron ion implantation applied to the surface of the structure using 150 KeV and a dosage of 5×10¹² atoms/cm². Subsequent high temperature processing step acts as annealing cycle. The structure now has the reach-through region 20 which connects the buried P region 18 with the surface of the silicon region.

The surface silicon dioxide layer is reoxidized and openings made through the surface oxide layer 17 for the resistor contact diffusions or ion implantations. The openings are made by conventional photolithography and etching techniques. The structure is placed, for example, in an ion implantation apparatus wherein phosphorus or arsenic ions of a dosage of 1×10¹⁵ atoms/cm² and power of 200 KeV are implanted into the structures to form the resistor contact regions 22. The wafers are annealed at 1000° C. for about 10-20 minutes in an inert ambient to remove the ion implantation damage and activate the impurities. The opening to the P+ reach-through 20 is made through the surface oxide 17 resulting in the FIG. 3 vertical structure and the FIG. 4 horizontal structure.

A suitable ohmic contact metal is then evaporated or deposited by other means onto the upper surface of the structure. Typical contact material is aluminum or aluminum-copper. However, other well known materials in the art can be used such as platinum, palladium, molybdenum, and so forth. Photolithography and etching techniques are utilized for the desired conductive lines on the surface of the semiconductor structure from the blanket layer.

It is preferred in the interest of high density that the one contact region 22 be contiguous to the dielectric barrier and one end of the silicon region. Also the reach-through region of the opposite conductivity 20 should be contiguous to the dielectric barrier at that end of the resistor structure.

Referring now to FIGS. 5 and 6 a second embodiment is illustrated wherein two resistors are formed in a single dielectrically isolated monocrystalline silicon region. The FIG. 5 structure is composed of silicon regions 30 separated from like silicon regions by a dielectric barrier 32 surrounding each of the regions 30. Each of these silicon regions 30 include base region 34 of a first conductivity, a second region 36 of a second conductivity, a third region 38 of the first conductivity buried within the second region 36, and a reach-through region 40 of the first conductivity connecting the surface of the silicon regions with the third region 38. The dielectric barrier 32 is composed preferably of at least an outer layer 42 of thermally grown silicon dioxide in an inert layer of pyrolytically grown silicon dioxide. In the FIG. 5, the first conductivity is P type and the second conductivity is N type which produces an N type resistor. The N+ contact regions for the surface resistor are indicated as 46. The N+ type contact regions for the buried resistor are indicated as contact regions 48. The second and buried resistor is located below the first conductivity buried region 38 and is indicated as principally region 50 with the diffused contact regions 48. The plane view of the present embodiment is shown in FIG. 6.

The FIG. 5 and FIG. 6 structure may be fabricated according to the same processes described with regard to FIGS. 1-4. However, additional space is required between the dielectric isolation region 32 and the buried P+ region 38 and reach-through contacts 40, so as to allow for the second resistor contact regions 48.

Referring now to FIGS. 7 and 8, there is shown the circuit diagram of the FIGS. 5 and 6 physical structure. FIG. 7 is the circuit of the surface resistor 56 with the contacts A, B and C given in FIG. 5. The diode 60 represents the PN junction between the region 38 and the region 50. FIG. 8 is the circuit representation for the buried resistor 50 which is located between contacts D and E. The isolating diode 60 is the PN junction between the region 38, 40 and the resistor region 50.

Referring now to FIG. 9, a third embodiment of the structure is shown wherein a masterslice type of personalization process is possible. A pattern of dielectric regions 70 in the silicon monocrystalline body isolate surface regions 72 of the body from one another. The monocrystalline silicon regions isolated from one another include a substrate of a first conductivity 74 for example, P type, and a region 74 of a second conductivity thereover. This region is typically grown by epitaxial techniques. A region of the first conductivity 78 is buried within the region of second conductivity 76. This region 78 is preferably formed by means of ion implantation as described above in regard to FIGS. 1-4. A reach-through 80 connects the buried region 78 with the surface. This reach-through is formed by either diffusion or ion implantation process. Second conductivity dopant, for example N+, is utilized to form contacts for the surface resistor contacts 82 and 84 and a contact for the N- region 76 below the P+ buried region 78. A choice can now be made at the time of personalization to either make a resistor utilizing the contacts 82 and 84 or to form a transistor utilizing the contact 84 as an emitter contact 80, as a base contact 86 and as the collector contact. In the case where a resistor is desired, the silicon dioxide layer 88 would cover the contact region 86 and no metal ohmic contact would be made to this portion of the silicon monocrystalline region. In the case that a transistor is desired as shown in FIG. 9 for illustrative purposes, the silicon dioxide layer 88 would cover one of the resistor contacts, for example contact 82. No ohmic contact would then be made to that portion of the region. FIG. 10 shows the circuit wherein 86 is the collector, 80 is the base and 84 is the emitter.

While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. 

What is claimed is:
 1. A high resistance structure for high density integrated circuits comprising:a silicon region separated from other silicon regions by a dielectric barrier surrounding said region; a first resistor of a first conductivity encompassing substantially the surface of said silicon region; electrical contacts to said first resistor; a region highly doped of a second conductivity located below said region of a first conductivity with reach-through of said highly doped second conductivity to the surface of the said region of a second conductivity and electric contacts thereto for biasing purposes; and a second resistor encompassing a region of said first conductivity located below said region of a second conductivity; reach-through regions of a first conductivity from the surface of said silicon region to said second resistor; and electrical contacts to said reach-through regions of a first conductivity.
 2. The resistance structure of claim 1 wherein said dielectric barrier is composed of at least an outer layer of thermally grown silicon dioxide.
 3. The resistance structure of claim 1 wherein said first conductivity is N, said second conductivity is P and said resistors are N-type.
 4. The resistance structure of claim 1 wherein said first conductivity is P, said second conductivity is N and said resistors are P-type.
 5. The resistance structure of claim 1 and further comprising in an adjacent said other silicon region an NPN transistor.
 6. The resistance structure of claim 1 and further comprising in an adjacent said other silicon region a PNP transistor.
 7. An integrated circuit structure comprising:silicon regions separated from like silicon regions by a dielectric barrier surrounding each of said regions; each of said silicon regions including a base region of a first conductivity, a second region over said base region of a second conductivity, a third region of said first conductivity buried within said second region so as to form electrically and physically separated upper and lower regions in said second region; and a reach-through region of said first conductivity connecting the surface of the silicon regions with said third region; means for electrically contacting said base, second upper, second lower and reach-through regions in said silicon regions to perform a desired circuit function; and said means for electrically connecting is so connected that a resistor is located in certain of said silicon regions, said resistor formed in said lower region of a second conductivity located below said third buried region of a first conductivity, said means for electrically contacting said lower region including reach-through regions of a second conductivity from the surface of said silicon region to said lower region of a second conductivity and electrical contacts thereto.
 8. The integrated circuit structure of claim 7 wherein said dielectric barrier is composed of at least an outer layer of thermally grown silicon dioxide.
 9. The integrated circuit structure of claim 7 wherein said first conductivity is N, said second conductivity is P, and said resistors are N-type.
 10. The integrated circuit structure of claim 7 wherein said first conductivity is P, said second conductivity is N, and said resistors are P-type.
 11. The integrated circuit structure of claim 7 wherein said means for electrically connecting is so connected that transistors are located within certain of said silicon regions other than wherein resistors are located, said first conductivity is N, said second conductivity is P, said transistors are PNP type and are located within said certain of said silicon regions.
 12. The integrated circuit structure of claim 7 wherein said means for electrically connecting is so connected that transistors are located within certain of said silicon regions other than wherein resistors are located, said first conductivity is P, said second conductivity is N, said transistors are NPN type and are located within certain of said silicon regions. 